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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD8021 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 low noise, high speed amplifier for 16-bit systems features low noise 2.1 nv/ hz input voltage noise 2.1 pa/ hz input current noise custom compensation constant bandwidth from g = C1 to g = C10 high speed 200 mhz, (g = C1) 190 mhz, (g = C10) low power 34 mw C 6.7 ma typ for 5 v supply output disable feature, 1.3 ma low distortion C93 db second harmonic, f c = 1 mhz C108 db third harmonic, f c = 1 mhz dc precision 1 mv max input offset voltage 0.5 v/ c input offset voltage drift wide supply range, 5 v to 24 v low price small packaging available in soic-8 and micro_soic-8 applications adc preamp and driver instrumentation preamp active filters portable instrumentation line receivers precision instruments ultrasound signal processing high gain circuits product description the AD8021 is a very high performance, high speed, voltage feedback amplifier that can be used in 16-bit resolution systems. it is designed to have low voltage and current noise (2.1 nv/ hz typ and 2.1 pa/ hz typ) while operating at the lowest quiescent supply current (7 ma @ 5 v) among t oday? h igh sp eed , lo w noise op amps. the AD8021 operates over a wide range of supply volta ges from 2.5 v to 12 v, as well as from single 5 v supplies, making it ideal for high- speed, low- power instruments. an output disable pin is provided that further reduces the quiescent supply current to 1.3 ma. the AD8021 allows the user to choose the gain bandwidth product that best suits the application. with a single capaci- tor, the user can compensate the AD8021 for the desired gain with little trade-off in bandwidth. the AD8021 is a very well-behaved amplifier that settles to 0.01% in 23 ns for a 1 v step. it has a fast overload recovery of 50 ns. the AD8021 is stable over temperature with low input offset voltage drift and input bias current drift, 0.5 v/ c and 10 na/ c, respectively. the AD8021 is also capable of driving a 75 ? line with 3 v video signals. not only is the AD8021 technically superior, but it is also priced considerably less than comparable amps drawing much higher quiescent current. the AD8021 is a high speed, general-purpose amplifier, ideal for a wide variety of gain configurations, and can be used throughout a signal processing chain and in control loops. the AD8021 is available in both standard 8-lead soic and micro_soic packages in the industrial temperature range of ?0 c to +85 c. frequency ?hz 0.1m 1g 1m 10m 100m closed-loop gain ?db 24 21 ? 18 15 12 9 6 3 0 ? v out = 50mv p-p g = ?, r f = 1k , r g = 200 , r in = 66.5 , c c = 1.5pf g = ?, r f = 499 , r g = 249 , r in = 63.4 , c c = 4pf g = ?, r f = 499 , r g = 499 , r in = 56.2 , c c = 7pf g = ?0, r f = 1k , r g = 100 , r in = 100 , c c = 0pf figure 1. small signal frequency response connection diagram soic-8 (r-8) micro_soic-8 (rm-8) 8 7 6 5 1 2 3 4 logic reference ?n +in ? s disable +v s v out c comp AD8021
rev. a ?2? AD8021especifications vs = AD8021ar/arm parameter conditions min typ max unit dynamic performance e3 db small signal bandwidth g = +1, c c = 10 pf, v o = 0.05 v p-p 355 490 mhz g = +2, c c = 7 pf, v o = 0.05 v p-p 160 205 mhz g = +5, c c = 2 pf, v o = 0.05 v p-p 150 185 mhz g = +10, c c = 0 pf, v o = 0.05 v p-p 110 150 mhz slew rate, 1 v step g = +1, c c = 10 pf 95 120 v/ s g = +2, c c = 7 pf 120 150 v/ s g = +5, c c = 2 pf 250 300 v/ s g = +10, c c = 0 pf 380 420 v/ s settling time to 0.01% v o = 1 v step, r l = 500 23 ns overload recovery (50%) 2.5 v input step, g = +2 50 ns distortion/noise performance f = 1 mhz hd2 v o = 2 v p-p e93 dbc hd3 v o = 2 v p-p e108 dbc f = 5 mhz hd2 v o = 2 v p-p e70 dbc hd3 v o = 2 v p-p e80 dbc input voltage noise f = 50 khz 2.1 2.6 nv/ hz input current noise f = 50 khz 2.1 pa/ hz differential gain error ntsc, r l = 150 0.03 % differential phase error ntsc, r l = 150 0.04 degrees dc performance input offset voltage 0.4 1.0 mv input offset voltage drift t min to t max 0.5 v/ c input bias current +input or einput 7.5 10.5 a input bias current drift 10 na/ c input offset current 0.1 0.5 a open-loop gain 82 86 db input characteristics input resistance 10 m common-mode input capacitance 1pf input common-mode voltage range e4.1 to +4.6 v common-mode rejection ratio v cm = 4 v e86 e98 db output characteristics output voltage swing e3.5 to +3.2 e3.8 to +3.4 v linear output current 60 ma short circuit current 75 ma capacitive load drive for 30% overshoot v o = 50 mv p-p/1 v p-p 15/120 pf disable characteristics off isolation f = 10 mhz e40 db turn-on time v o = 0 v to 2 v, 50% logic to 50% output 45 ns turn-off time v o = 0 v to 2 v, 50% logic to 50% output 50 ns disable voltage?off/on v disable e v logic reference 1.75/1.90 v enabled leakage current logic ref = 0.4 v 70 a disable = 4.0 v 2 a disabled leakage current logic ref = 0.4 v 30 a disable = 0.4 v 33 a power supply operating range 2.25 5 12.0 v quiescent current output enabled 7.0 7.7 ma output disabled 1.3 1.6 ma +power supply rejection ratio v cc = 4 v to 6 v, v ee = e5 v e86 e95 db epower supply rejection ratio v cc = 5 v, v ee = e6 v to e4 v e86 e95 db specifications subject to change without notice. (@ t a = 25 c, r l = 1 k , gain = +2, unless otherwise noted.) v s = 5 v
rev. a specifications vs = AD8021 ?3? (@ t a = 25 c, r l = 1 k , gain = +2, unless otherwise noted.) AD8021ar/arm parameter conditions min typ max unit dynamic performance e3 db small signal bandwidth g = +1, c c = 10 pf, v o = 0.05 v p-p 520 560 mhz g = +2, c c = 7 pf, v o = 0.05 v p-p 175 220 mhz g = +5, c c = 2 pf, v o = 0.05 v p-p 170 200 mhz g = +10, c c = 0 pf, v o = 0.05 v p-p 125 165 mhz slew rate, 1 v step g = +1, c c = 10 pf 105 130 v/ s g = +2, c c = 7 pf 140 170 v/ s g = +5, c c = 2 pf 265 340 v/ s g = +10, c c = 0 pf 400 460 v/ s settling time to 0.01% v o = 1 v step, r l = 500 21 ns overload recovery (50%) 6 v input step, g = +2 90 ns distortion/noise performance f = 1 mhz hd2 v o = 2 v p-p e95 dbc hd3 v o = 2 v p-p e116 dbc f = 5 mhz hd2 v o = 2 v p-p e71 dbc hd3 v o = 2 v p-p e83 dbc input voltage noise f = 50 khz 2.1 2.6 nv/ hz input current noise f = 50 khz 2.1 pa/ hz differential gain error ntsc, r l = 150 0.03 % differential phase error ntsc, r l = 150 0.04 degrees dc performance input offset voltage 0.4 1.0 mv input offset voltage drift t min to t max 0.2 v/ c input bias current +input or einput 8 11.3 a input bias current drift 10 na/ c input offset current 0.1 0.5 a open-loop gain 84 88 db input characteristics input resistance 10 m common-mode input capacitance 1pf input common-mode voltage range e11.1 to +11.6 v common-mode rejection ratio v cm = 10 v e86 e96 db output characteristics output voltage swing e10.2 to +9.8 e10.6 to +10.2 v linear output current 70 ma short circuit current 115 ma capacitive load drive for 30% overshoot v o = 50 mv p-p/1 v p-p 15/120 pf disable characteristics off isolation f = 10 mhz e40 db turn-on time v o = 0 v to 2 v, 50% logic to 50% output 45 ns turn-off time v o = 0 v to 2 v, 50% logic to 50% output 50 ns disable voltage?off/on v disable e v logic reference 1.80/1.95 v enabled leakage current logic ref = 0.4 v 70 a disable = 4.0 v 2 a disabled leakage current logic ref = 0.4 v 30 a disable = 0.4 v 33 a power supply operating range 2.25 5 12.0 v quiescent current output enabled 7.8 8.6 ma output disabled 1.7 2.0 ma +power supply rejection ratio v cc = +11 v to +13 v, v ee = e12 v e86 e96 db epower supply rejection ratio v cc = +12 v, v ee = e13 v to e11 v e86 e100 db specifications subject to change without notice. v s = 12 v
rev. a ?4? AD8021especifications vs = AD8021ar/arm parameter conditions min typ max unit dynamic performance e3 db small signal bandwidth g = +1, c c = 10 pf, v o = 0.05 v p-p 270 305 mhz g = +2, c c = 7 pf, v o = 0.05 v p-p 155 190 mhz g = +5, c c = 2 pf, v o = 0.05 v p-p 135 165 mhz g = +10, c c = 0 pf, v o = 0.05 v p-p 95 130 mhz slew rate, 1 v step g = +1, c c = 10 pf 80 110 v/ s g = +2, c c = 7 pf 110 140 v/ s g = +5, c c = 2 pf 210 280 v/ s g = +10, c c = 0 pf 290 390 v/ s settling time to 0.01% v o = 1 v step, r l = 500 28 ns overload recovery (50%) 0 v to 2.5 v input step, g = +2 40 ns distortion/noise performance f = 1 mhz hd2 v o = 2 v p-p e84 dbc hd3 v o = 2 v p-p e91 dbc f = 5 mhz hd2 v o = 2 v p-p e68 dbc hd3 v o = 2 v p-p e81 dbc input voltage noise f = 50 khz 2.1 2.6 nv/ hz input current noise f = 50 khz 2.1 pa/ hz dc performance input offset voltage 0.4 1.0 mv input offset voltage drift t min to t max 0.8 v/ c input bias current +input or einput 7.5 10.3 a input bias current drift 10 na/ c input offset current 0.1 0.5 a open-loop gain 72 76 db input characteristics input resistance 10 m common-mode input capacitance 1pf input common-mode voltage range 0.9 to 4.6 v common-mode rejection ratio 1.5 v to 3.5 v e84 e98 db output characteristics output voltage swing 1.25 to 3.38 1.10 to 3.60 v linear output current 30 ma short circuit current 50 ma capacitive load drive for 30% overshoot v o = 50 mv p-p/1 v p-p 10/120 pf disable characteristics off isolation f = 10 mhz e40 db turn-on time v o = 0 v to 1 v, 50% logic to 50% output 45 ns turn-off time v o = 0 v to 1 v, 50% logic to 50% output 50 ns disable voltage?off/on v disable e v logic reference 1.55/1.70 v enabled leakage current logic ref = 0.4 v 70 a disable = 4.0 v 2 a disabled leakage current logic ref = 0.4 v 30 a disable = 0.4 v 33 a power supply operating range 2.25 5 12.0 v quiescent current output enabled 6.7 7.5 ma output disabled 1.2 1.5 ma +power supply rejection ratio v cc = 4.5 v to 5.5 v, v ee = 0 v e74 e82 db epower supply rejection ratio v cc = +5 v, v ee = e0.5 v to +0.5 v e76 e84 db specifications subject to change without notice. (@ t a = 25 c, r l = 1 k , gain = +2, unless otherwise noted.) v s = 5 v
rev. a AD8021 ?5? caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD8021 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 v power dissipation . . . . . . . . observed power derating curves input voltage (common-mode) . . . . . . . . . . . . . . . v s 1 v differential input voltage 2 . . . . . . . . . . . . . . . . . . . . . . 0.8 v differential input current . . . . . . . . . . . . . . . . . . . . . . 10 ma output short circuit duration . . . . . . . . . . . . . . . . . . .o bserved power derating curves storage temperature . . . . . . . . . . . . . . . . . . e65 c to +125 c operating temperature range . . . . . . . . . . . e40 c to +85 c lead temperature range (soldering, 10 sec) . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 the AD8021 inputs are protected by diodes. current-limiting resistors are not used in order to preserve the low noise. if a differential input exceeds 0.8 v, the input current should be limited to 10 ma. maximum power dissipation t he maximum power that can be safely dissipated by the AD8021 is limited by the associated rise in junction temperature. the maximum safe junction temperature for plastic encapsu lated devices is determined by the glass transition temperature of the plastic, approximately 150 c. temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junc- tion temperature of 175 c for an extended period can result in device failure. w hile the AD8021 is internally short circuit protected, this m ay not be sufficient to guarantee that the maximum junction temperature (150 c) is not exceeded under all conditions. to ensure proper operation, it is necessary to observe the maximum power derating curves. pin function descriptions pin no. mnemonic function 1 logic reference r eference for pin 8 * voltage level. connect to logic low supply. 2 ein inverting input 3 +in noninverting input 4ev s negative supply voltage 5c comp compensation capacitor. tie to ev s . (see the applications section for value.) 6v out output 7+v s positive supply voltage 8 disable disable, active low * * when pin 8 ( disable ) is about two or more volts higher than pin 1 (logic reference), the part is enabled. when pin 8 is brought down to within about 1.5 v of pin 1, the part is disabled. (see the specification tables for exact disable and enable voltage levels.) if the disable feature is not going to be used, pin 8 can be tied to +v s or a logic high source, and pin 1 can be tied to ground or logic low. alternatively, if pin 1 and pin 8 are not connected, the part will be in an enabled state. ordering guide model temperature range package description package outline branding information AD8021ar e40 c to +85 c 8-lead soic so-8 AD8021ar-reel e40 c to +85 c 8-lead soic so-8 AD8021ar-reel7 e40 c to +85 c 8-lead soic so-8 AD8021arm e40 c to +85 c 8-lead micro_soic rm-8 hna AD8021arm-reel e40 c to +85 c 8-lead micro_soic rm-8 hna AD8021arm-reel7 e40 c to +85 c 8-lead micro_soic rm-8 hna AD8021ar-eval evaluation board so-8 ambient temperature e c 1.5 1.0 0 e50 80 e40 power dissipation e w e30 e20 e10 010 20 30 40 50 60 70 0.5 90 8-lead soic 8-lead soic package t j = 150 c figure 2. maximum power dissipation vs. temperature* * specification is for device in free air: 8-lead soic: ja = 160 c/w 8-lead micro_soic: ja = 200 c/w pin configuration 8 7 6 5 1 2 3 4 logic reference ein +in ev s disable +v s v out c comp AD8021
rev. a AD8021 ?6? etypical performance characteristics (t a = 25 c, v s = 5 v, r l = 1 k , g = +2, r f = r g = 499 , r s = 49.9 , r o = 976 , r d = 53.6 , c c = 7 pf, c l = 0, c f = 0, v out = 2 v p-p, freq = 1 mhz, unless otherwise noted.) frequency e hz 0.1m 1g 1m 10m 100m closed-loop gain e db 24 21 e6 18 15 12 9 6 3 0 e3 g = 1, r f = 75 , c c = 10pf g = 5, r f = 1k , r g = 249 , c c = 2pf g = 10, r f = 1k , r g = 110 , c c = 0pf g = 2, r f = r g = 499 , c c = 7pf tpc 1. small signal frequency response vs. frequency and gain, v out = 50 mv p-p, nonin- verting. see test circuit 1. frequency e hz 0.1m 1g 1m 10m 100m gain e db 24 21 e6 18 15 12 9 6 3 0 e3 g = e5, r f = 1k , r g = 200 , r in = 66.5 , c c = 1.5pf g = e2, r f = 499 , r g = 249 , r in = 63.4 , c c = 4pf g = e1, r f = 499 , r g = 499 , r in = 56.2 , c c = 7pf g = e10, r f = 1k , r g = 100 , r in = 100 , c c = 0pf tpc 2. small signal frequency response vs. frequency and gain, v out = 50 mv p-p, invert- ing. see test circuit 1. frequency e hz 0.1m 1g 1m gain e db 10m 100m 9 8 e1 7 6 5 4 3 2 1 0 g = 2 c c = 5pf 7pf 7pf 9pf 9pf tpc 3. small signal frequency response vs. frequency and compensation capacitor, v out = 50 mv p-p. see test circuit 1. frequency e hz 1g 1m gain e db 10m 100m 9 8 e1 7 6 5 4 3 2 1 0 g = 2 v s = 2.5v 5v v s = 2.5v 12v tpc 4. small signal frequency response vs. frequency and supply, v out = 50 mv p-p, non- inverting. see test circuit 1. frequency e hz 1g 1m gain e db 10m 100m 3 2 e7 1 0 e1 e2 e3 e4 e5 e6 g = e1 v s = 2.5v 5v v s = 2.5v v s = 12v tpc 5. small signal frequency response vs. frequency and supply, v out = 50 mv p-p, inverting. see test circuit 3. frequency e hz 1g 1m gain e db 10m 100m 9 8 e1 7 6 5 4 3 2 1 0 g = 2 v out = 0.1v and 50mv p-p v out = 4v p-p 1v p-p tpc 6. frequency response vs. frequency and v out , noninverting. see test circuit 1.
rev. a AD8021 ?7? frequency e hz 0.1m 1g 1m gain e db 10m 100m 9 8 7 6 5 4 3 2 1 0 g = 2 r l = 100 1k 10 tpc 7. large signal frequency response vs. frequency and load, noninverting. see test circuit 2. frequency e hz 1g 1m gain e db 10m 100m 9 8 7 6 5 4 3 2 1 0 g = 2 +85 c v out = 50mv p-p e40 c +25 c +85 c e40 c +25 c e1 v out = 2v p-p tpc 8. frequency response vs. frequency temperature and v out , noninverting. see test circuit 1. frequency e hz 1g 1m gain e db 10m 100m 15 12 9 6 3 0 e3 e6 e9 e12 g = 2 18 50pf 30pf 20pf 10pf 0pf tpc 9. small signal frequency response vs. frequency and capacitive load, noninverting, v out = 50 mv p-p. see test circuit 2 and figure 16. frequency e hz 1g 0.1m 10m 100m gain e db 9 8 7 6 5 4 3 2 1 0 g = 2 r f = r g 10 r f = 1k r f = 499 r f = 250 r f = 150 r f = 75 r f = 1k and c f = 2.2pf 1m tpc 10. small signal frequency response vs. frequency and r f , noninverting, v out = 50 mv p- p. see test circuit 1. frequency e hz 0.1m 1g 1m gain e db 10m 100m 12 9 6 3 0 e3 e6 e9 e12 e15 g = 2 r s = 49.9 15 r s = 100 r s = 249 tpc 11. small signal frequency response vs. frequency and r s , noninverting. v out = 50 mv p-p. see test circuit 1. frequency e hz 100k 1g 1m open-loop gain e db 10m 100m 100 90 80 70 60 50 40 30 20 10 0 phase e degrees 90 45 0 e45 e90 e135 135 180 10k tpc 12. open-loop gain and phase vs. frequency. r g =100 , r f = 1 k , r o = 976 , r d = 53.6, c c = 0 pf. see test circuit 3.
rev. a AD8021 ?8? frequency e hz 1m gain e db 10m 100m 6.2 6.0 5.8 5.6 5.4 g = 2 6.4 v s = 2.5v 5v 12v tpc 13. 0.1 db flatness vs. frequency and sup- ply, v out = 1 v p-p, r l = 150 . noninverting, see test circuit 2. frequency e hz 0.1m distortion e dbc 1m e40 e60 e90 e110 e130 e20 e30 e50 e70 e80 e100 e120 10m r l = 100 r l = 1k e3rd 2nd 20m tpc 14. second and third harmonic distortion vs. frequency and r l frequency e hz 100k distortion e dbc 1m 20m e40 e60 e90 e110 e130 e30 e50 e70 e80 e100 e120 10m v s = 2.5v 2nd 3rd v s = 12v v s = 5v 3rd 3rd 2nd 2nd tpc 15. second and third harmonic distortion vs. frequency and v s ?8? frequency e mhz 9.5 p out e dbm 10 10.5 e40 e60 e90 e110 e30 e50 e70 e80 e100 e120 e20 9.7 10.3 f = 0.2mhz f 1 f 2 976 53.6 50 p out tpc 16. intermodulation distortion vs. frequency frequency e mhz 0 third-order intercept e dbm 10 20 45 30 25 40 35 20 50 515 v s = 5v v s = 2.5v tpc 17. third-order intercept vs. frequency and supply voltage v out e v p-p 1 distortion e dbc 35 e60 e90 e100 e70 e80 e120 e50 24 2nd 6 e110 3rd 2nd 3rd r l = 1k r l = 100 tpc 18. second and third harmonic distortion vs. v out and r l
rev. a AD8021 ?9? v out e v p-p 1 distortion e dbc 35 e60 e90 e100 e70 e80 e120 e50 24 2nd 6 e110 3rd 2nd 3rd f c = 1mhz f c = 5mhz tpc 19. second and third harmonic distortion vs. v out and fundamental frequency (f c ), g = +2 v out e v p-p 1 distortion e dbc 35 e60 e90 e100 e70 e80 e50 24 2nd 6 e110 3rd 2nd 3rd f c = 5mhz f c = 1mhz e40 tpc 20. second and third harmonic distortion vs. v out and fundamental frequency (f c ), g = +10 feedback resistance e 0 distortion e dbc 400 800 e90 e110 e80 200 600 2nd 1000 e120 3rd e70 e100 f c = 1mhz r l = 1k tpc 21. second and third harmonic distortion vs. feedback resistor (r f ) load e 0 positive output voltage e v 800 1600 3.2 2.9 3.4 400 1200 2000 2.8 3.5 3.1 3.3 3.0 negative output voltage e v e3.4 e3.7 e3.2 e3.8 e3.1 e3.5 e3.3 e3.6 negative output positive output tpc 22. dc output voltage vs. load. see test circuit 1. temperature e c e50 e10 30 e30 10 50 70 90 110 60 0 100 120 40 80 20 v s = 2.5 v s = 5.0 v s = 12 short-circuit current e ma tpc 23. short-circuit current to ground vs. temperature r l = 1k , 150 v out e mv 50 40 30 20 10 e10 e20 e30 e40 e50 g = 2 04080 120 160 200 time e ns tpc 24. small signal transient response vs. r l , v o = 50 mv p-p. see test circuit 2, non- inverting.
rev. a ?10? AD8021 v o = 4v p-p g = 2 r l = 1k r l = 150 v out e v 2.0 1.0 e1.0 e2.0 04080 120 160 200 time e ns tpc 25. large signal transient response vs. r l . see test circuit 2, noninverting. v o = 4v p-p g = e1 v out v in 5 4 3 2 1 e1 e2 e3 e4 e5 volts 050 100 150 200 250 time e ns tpc 26. large signal transient response. see test circuit 3, inverting. 2.0 1.0 e1.0 e2.0 v out e v v o = 4v p-p c l = 50pf g = 2 c l = 10pf, 0pf 04080 120 160 200 time e ns tpc 27. large signal transient response vs. c l . see test circuit 1. ?10? v o = 2v p-p g = 2 v s = 5v v s = 2.5v v out e v 2.0 1.0 e1.0 e2.0 04080 120 160 200 time e ns tpc 28. large signal transient response vs. v s . see test circuit 1. v in = 3v g = +2 v out, r l = 1k v in = 1v/div v out = 2v/div v in r l = 150 0 100 200 300 400 500 time e ns tpc 29. overdrive recovery vs. r l . see test circuit 2. 25ns e0.01% +0.01% hor = 5ns/div vert = 0.2mv/div g = 2 output settling tpc 30. 0.01% settling time, 2 v step
rev. a AD8021 ?11? time e s 432 12 settling e v 20 28 e100 0816 24 e80 e60 e40 e20 0 20 40 60 80 100 t 1 5v 0v pulse width = 300 s pulse width = 120ns tpc 31. long-term settling, 0 v to 5 v, v s = 12 v, g = +13 g = 1 50 40 30 20 10 e10 e20 e30 e40 e50 04080 120 160 200 time e ns v out e mv tpc 32. small signal transient response, v o = 50 mv p-p. g = +1. see test circuit 1. 10m frequency e hz 100 10 1 10 100 1k 10k 100k 1m vo ltag e noise e nv/ hz 2.1nv/ hz tpc 33. input voltage noise vs. frequency frequency e hz 100 10m 1k input current noise e pa/ hz 10k 100k 100 1 10 10 1m tpc 34. input current noise vs. frequency temperature e c e25 100 25 vo lta ge offset e mv 50 75 0.48 0.24 e50 0 0.44 0.40 0.36 0.32 0.28 tpc 35. v os vs. temperature temperature e c e25 100 25 input bias current e a 50 75 8.4 6.0 e50 0 8.0 7.6 7.2 6.8 6.4 tpc 36. input bias current vs. temperature
rev. a AD8021 ?12? frequency e hz 100k 10m cmrr e db 100m e20 10k 1m e30 e40 e50 e60 e70 e80 e90 e100 e110 e120 tpc 37. cmrr vs. frequency. see test circuit 4. frequency e hz 100k 1g 10m output impedance e 100m 300 10k 1m 100 30 10 3 1 0.3 0.1 0.03 0.01 0.003 tpc 38. output impedance vs. frequency, chip enabled. see test circuit 5. disable t dis = 50ns v output 4v 2v 2v 1v t en = 45ns 0 100 200 300 400 500 time e ns tpc 39. enable (t en )/disable (t dis ) time vs. v out . see test circuit 6. frequency e hz 1m 1g disabled isolation e db 100m 0 0.1m 10m e10 e20 e30 e40 e50 e60 e70 e80 e90 e100 tpc 40. input to output isolation, chip disabled. see test circuit 7. frequency e hz 100k 1g output impedance e 10m 300k 10k 1m 100k 30k 10k 3k 1k 300 100 30 10 3 100m tpc 41. output impedance vs. frequency, chip disabled. see test circuit 8. frequency e hz 1m 500m psrr e db 100m 0 10k 10m e10 e30 e50 e70 e80 e100 100k e20 e40 e60 e90 v s = 2.5v v s = 5v v s = 12v + psrr epsrr tpc 42. psrr vs. frequency and supply voltage. see test circuits 9 and 10.
rev. a AD8021 ?13? 50 ev s c c +v s 5 r s r o r d r f c f r g 49.9 r in 50 cable 50 cable test circuit 1. noninverting gain r f c f r g r l r s 49.9 r in c c c l fet probe 50 ev s +v s 5 50 cable test circuit 2. noninverting gain with fet probe r f r o r d 49.9 r g r in 49.9 50 ev s c c +v s 5 50 cable 50 cable test circuit 3. inverting gain test circuits hp8753d 50 AD8021 499 499 55.6 499 499 49.9 network analyzer ev s c c 5 +v s 7pf 50 test circuit 4. cmrr AD8021 r f 499 100 7pf ev s c c +v s 5 network analyzer hp8753d r g 499 50 test circuit 5. output impedance, chip enabled 499 AD8021 49.9 49.9 7pf ev s c c 5 976 1 8 1.0v 49.9 499 +v s disable logic ref 4v 53.6 test circuit 6. enable/disable temperature e c 0 100 supply current e ma 50 8.5 e50 25 8.0 7.5 7.0 6.5 6.0 5.5 75 e25 tpc 43. quiescent supply current vs. temperature
rev. a AD8021 ?14? 499 AD8021 49.9 49.9 ev s c c 7pf 5 1 8 499 network analyzer 50 1k fet probe +v s logic ref disable hp8753d 50 cable 50 test circuit 7. input to output isolation, chip disabled +v s AD8021 100 1 8 network analyzer ev s c c 7pf 5 hp8753d 50 test circuit 8. output impedance, chip disabled 499 499 network analyzer 249 976 53.6 49.9 , 5w +v s 50 ev s c c 7pf 5 hp8753d +v s 50 cable bias bnc 50 test circuit 9. positive psrr +v s network analyzer 50 249 976 499 499 53.6 ev s 49.9 5w c c 7pf 5 hp8753d e v s bias bnc 50 cable 50 test circuit 10. negative psrr
rev. a AD8021 ?15? using the AD8021 the typical voltage feedback op amp is frequency stabilized with a fixed internal capacitor, c internal , using dominant pole compensation. to a first-order approximation, voltage feed back op amps have a fixed gain bandwidth product. for example, if its e3 db bandwidth for g = +1 is 200 mhz, at a gain of g = +10, its bandwidth will be only about 20 mhz. the AD8021 is a volt- age feedback op amp with a minimal c internal of about 1.5 pf. by adding an external compensation capacitor, c c , the user can circumvent the fixed gain bandwidth limitation of other voltage feedback op amps. unlike the typical op amp with fixed compensation, the AD8021 allows the user to: 1. maximize the amplifier bandwidth for closed-loop gains between 1 and 10, avoiding the usual loss of bandwidth and slew rate. 2. optimize the trade-off between bandwidth and phase margin for a particular application. 3. match bandwidth in gain blocks with different noise gains, such as when designing differential amplifiers (as shown in figure 11 of the applications section). frequency e hz 1m open-loop gain e db 100m 110 10k 10m 100 80 60 40 30 10 100k 90 70 50 20 c c = 10pf 1k 1g 10g 0 e10 180 135 45 90 0 phase e degrees c c = 0pf (b) (c) (a) (a) (b) (c) 86 figure 3. simplified diagram of open-loop gain and phase response figure 3 is the AD8021 gain and phase plot that has been sim- plified for instructional purposes. if the desired closed-loop gain is g = +1 and c c = 10 pf is chosen, arrow a of the figure shows that the bandwidth is about 200 mhz and the phase margin is about 60 . if the gain is changed to g = +10 and c c fixed at 10 pf, then (as expected for a typical op amp) the bandwidth is degraded to about 20 mhz and the phase margin increases to 90 (arrow b). however, by reducing c c to zero, the bandwidth and phase margin return to about 200 mhz and 60 (arrow c), respectively. in addition, the slew rate is dramatically increased, as it roughly varies with the inverse of c c . 1234567891011 1 2 3 4 5 6 7 8 9 10 0 noise gain e v/v compensation capacitance e pf figure 4. suggested compensation capacitance vs. gain for maintaining 1 db peaking table i and figure 4 provide lists recommending values of compensation capacitance at various gains and the corresponding slew rate, bandwidth, and noise. note that the value of the compensation capacitor depends on the circuit noise gain, not the voltage gain. as shown in figure 5, the noise gain, g n , of an op amp gain block is equal to its noninverting voltage gain, regardless of whether it is actually used for inverting or nonin- verting gain. thus, noninverting g r r inverting g r r nfg nfg =+ =+ / / 1 1 AD8021 c comp 3 2 ev s 5 6 r f 800 r g 200 + e g = g n = 5 AD8021 c comp 2 3 ev s 5 6 e + g = e4 g n = 5 r f 800 r g 200 r s noninverting inverting 1 figure 5. the noise gain of both is five table i. recommended component values. see test circuit 2. c f = c l = 0, r l = 1 k , r in = 49.9 . noise gain slew e3 db output noise output noise (noninverting r s r f r g c comp rate ss bw (AD8021 only) (AD8021 with resistors) gain) ( )( )( ) (pf) (v/ s) (mhz) (nv/ hz hz
rev. a AD8021 ?16? with the AD8021, a variety of trade-offs can be made to fine- tune its dynamic performance. sometimes more bandwidth or slew rate is needed at a particular gain. reducing the compen- sation capacitance, as illustrated in tpc 3, will increase the bandwidth and peaking due to a decrease in phase margin. on the other hand, if more stability is needed, increasing the compensation cap will decrease the bandwidth while increas- ing the phase margin. as with all high-speed amplifiers, parasitic capacitance and inductance around the amplifier can affect its dynamic response. often the input capacitance (due to the op amp itself, as well as the pc board) could have a significant effect. the feedback resistance, together with the input capacitance, may contrib ute to a loss of phase margin, thereby affecting the high-frequency response, as shown in tpc 10. furthermore, a capacitor (c f ) in parallel with the feedback resistor can compensate for this phase loss. additionally, any resistance in series with the source will create a pole with the input capacitance (as well as dampen high-frequency resonance due to package and board inductance and capacitance), the effect of which is shown in tpc 11. it must also be noted that increasing resistor values will increase the overall noise of the amplifier, and that reducing the feedback resistor value will increase the load on the output stage, thus increasing distortion (tpc 18). using the disable feature when pin 8 ( disable ) is approximately two or more volts higher than pin 1 (logic reference), the part is enabled. when pin 8 is brought down to within about 1.5 v of pin 1, the part is disabled. see the specification tables for exact disable and enable voltage levels. if the disable feature is not going to be used, pin 8 can be tied to v s or a logic high source, and pin 1 can be tied to ground or logic low. alternatively, if pin 1 and pin 8 are not connected, the part will be in an enabled state. theory of operation the AD8021 is fabricated on the second generation of analog devices? proprietary high voltage extra-fast complementary bipolar (xfcb) process, which enables the construction of pnp and npn transistors with similar f t ?s in the 3 ghz region. the transistors are dielectrically isolated from the substrate (and each other), eliminating the parasitic and latch-up problems caused by junction isolation. it also reduces the nonlinear capacitance (a source of distortion) and allows a higher tran- sistor f t for a given quiescent current. the supply current is trimmed, which results in less part-to-part variation of band- width, slew rate, distortion, and settling time. as shown in figure 6, the AD8021 input stage consists of an npn differential pair in which each transistor operates at 0.8 ma collec- tor current. this allows the input devices a high transconductance and hence, the AD8021 has a low input noise of 2.1 nv/ hz @ 50 khz. the input stage drives a folded cascode that consists of a pair of pnp transistors. the folded cascode and current mirror provide a differential to single-ended conversion of signal current. this current then drives the high-impedance node (pin 5), where the c c external capacitor is connected. the output stage pre serves this high impedance with a current gain of 5,000, so that the AD8021 can maintain a high open-loop gain, even when driving heavy loads. two internal diode clamps across the inputs (pins 2 and 3) protect the input transistors from large voltages that could otherwise cause emitter-base breakdown, which would result in degradation of offset-voltage and input bias current. c c output +v s ev s +in ein c internal 1.5pf c comp figure 6. simplified schematic pcb layout considerations as with all high-speed op amps, achieving optimum perfor mance from the AD8021 requires careful attention to pc board layout. particular care must be exercised to minimize lead lengths between the ground leads of the bypass capacitors and between the compensation capacitor and the negative supply. otherwise, lead inductance can influence the frequency response and even cause high-frequency oscillations. use of a multilayer printed circuit board, with an internal ground plane, will reduce ground noise and enable a compact component arrangement. due to the relatively high impedance of pin 5, and low values of the compensation capacitor, a guard ring is recommended. the guard ring is simply a pc trace that encircles pin 5 and is con nected to the output, pin 6, that is at the same potential as pin 5. this serves two functions. it shields pin 5 from any local cir- cuit noise generated by surrounding circuitry. it also minimizes stray capacitance, which would tend to otherwise reduce the band- width. an example of a guard ring layout may be seen in figure 7. also shown in f igure 7, the compensation capacitor is located immediately adjacent to the edge of the AD8021 package, span- ning pin 4 and pin 5. this capacitor must be a high-quality surface-mount cog or npo ceramic. the use of leaded capaci- tors is not recommended. the high-frequency bypass capacitor(s) should be located immediately adjacent to the suppl ies, pins 4 and 7. to achieve the shortest possible lead length at the inverting input, the feedback resistor r f is located beneath the board and just spans the distance from the output, pin 6, to inverting input pin 2. the return node of resistor r g should be situated as closely as possible to the return node of the negative supply bypass capacitor connected to pin 4.
rev. a AD8021 ?17? table ii. summary of adc driver performance, f c = 65 khz, v out = 10 v p-p parameter measurement unit second harmonic distortion e101.3 db third harmonic distortion e109.5 db thd e100.0 db sfdr 100.3 db figure 9 shows another adc driver connection. the circuit was tested with a noninverting gain of 10.1 and an output voltage of approximately 20 v p-p for optimum resolution and noise per- formance. no filtering was used. an fft was performed using analog devices? evaluation software for the ad7665 16-bit con- verter. the results are listed in table iii. 50 5v AD8021 + e e12v +12v ad7665 570 ksps 16 bits 50 3 2 r f 750 optional c f in lo in 6 50 hi adc c c 5 r g 82.5 figure 9. no ninverting adc driver, gain = 10, f c = 100 khz table iii. summary of adc driver performance, f c = 100 khz, v out = 20 v p-p parameter measurement unit second harmonic distortion e92.6 db third harmonic distortion e86.4 db thd e84.4 db sfdr 5.4 db differential driver the AD8021 is uniquely suited as a low-noise differential driver for many adcs, balanced lines, and other applications requir- i ng differential drive. if pairs of internally compensated op amps are configured as inverter and follower, the noise gain of the inverter will be higher than that of the follower section, result- ing in an imbalance in the frequency response (see figure 11). a better solution takes advantage of the external compensation feature of the AD8021. by reducing the c comp value of the inverter, its bandwidth may be increased to match that of the f ollower, avoiding compromises in gain bandwidth and phase delay. the inverting and noninverting bandwidths can be closely matched using the compensati on feature, t hus m inimizing distortion. disable v out 8 7 6 1 2 3 logic reference ein +in ev s 4 +v s 5 bypass capacitor ground plane compensation capacitor ground plane (top view) bypass capacitor metal c comp figure 7. recommended location of critical components and guard ring driving 16-bit adc converters low noise and adjustable compensation make the AD8021 especially suitable as a buffer/driver for high-resolution a-to-d converters. as seen in tpc 15, the harmonic distortion is better than 90 db at frequencies between 100 khz and 1 mhz. this is a real advantage for complex waveforms that contain high- frequency information, as the phase and gain integrity of the sa mp led waveform can be preserved throughout the conversion process. the increase in loop gain results in improved output regulation and lower noise when the converter input changes state during a ?sample.? this advantage is particularly appar- en t whe n u sin g 16-bit high-resolution a/d converters, with high sampling rates. figure 8 shows a typical adc driver configuration. the AD8021 is in an inverting gain of e7.5, f c is 65 khz, and its output voltage is 10 v p-p. the results are listed in table ii. 50 5v AD8021 + e e12v +12v ad7665 570 ksps 16 bits 590 3 2 r f 1.5k in lo in 6 hi c c 5 10pf 56pf r g 200 65khz figure 8. inverting adc driver, gain = ?7.5, f c = 65 khz
rev. a AD8021 ?18? figure 10 illustrates an inverter-follower driver circuit operating at a gain of two, using individually compensated AD8021s. the values of feedback and load resistors were selected to provide a total load of less than 1 k , and the equivalent resistances seen at each op amp?s inputs were matched to minimize offset voltage and drift. figure 12 is a plot of the resulting ac responses of driver halves. AD8021 + e 3 2 6 7pf 249 499 g = +2 499 49.9 1k v out1 5 ev s AD8021 + e 3 2 6 5pf 232 g = e2 664 1k v out2 5 ev s 332 v in figure 10. differential amplifier g = e2 g = +2 gain e db frequency e hz 100k 1m 10m 100m 1g 12 9 6 3 0 e3 e6 e9 e12 e15 e18 figure 11. ac response of two identically compensated high-speed op amps configured for gains of +2 and ?2 g = 2 100k 1m 10m 100m 1g frequency e hz 12 9 6 3 0 e3 e6 e9 e12 e15 e18 gain e db figure 12. ac response of two dissimilarly compensated AD8021 op amps (figure 11) configured for gains of +2 and ?2. note the close gain match using the AD8021 in active filters the low noise and high gain bandwidth of the AD8021 make it an exce llent choice in active filter circuits. most active filter literature provides resistor and ca pacitor values for various fi lters but neglects the effect of the op amp?s finite bandwidth on filter performance; ideal filter response with infinite loop gain is implied. unfortu nately, real filters do not behave in this manner. instead, they exhibit finite limits of attenuation, depending on the gain bandwidth of the active device. good low-pass filter performance requires an op amp with high gain bandwidth for attenuation at high frequencies, and low noise and high dc gain for low-frequency pass-band performance. figure 13 shows the schematic of a 2-pole, low-pass active filter, and table iv lists typical component values for filters having a bessel -type response with gains of 2 and 5. figure 14 is a net- work analyzer plot of this filter?s performance. c c c2 AD8021 3 2 r f 6 v out r g +v s r2 r1 v in 5 ev s c1 figure 13. schematic of a second-order low-pass active filter table iv. typical component values for second-order low- pass filter of figure 13 gain r1 ( ) r2 ( )r f ( )r s ( )c1 c2 c c 2 71.5 215 499 499 10 nf 10 nf 7 pf 5 44.2 365 90.9 365 10 nf 10 nf 2 pf 1k 10k 100k 1m 10m frequency e hz 50 40 30 20 10 0 e10 e20 e30 e40 e50 gain e db g = 2 g = 5 figure 14. frequency response of the filter circuit of figure 13 for two different gains
rev. a AD8021 ?19? driving capacitive loads when the AD8021 drives a capacitive load, the high-frequency response may show excessive peaking before it rolls off. two techniques can be used to improve stability at high frequency and reduce peaking. the first technique is to increase the compen- sation capacitor, c c , which reduces the peaking while m aintaining gain flatness at low frequencies. the second technique is to add a resistor, r snub , in series between the output pin of the AD8021 and the capacitive load, c l . figure 15 shows the response of the AD8021 when both c c and r snub are used to reduce peaking. for a given c l , figure 16 can be used to determine the value of r snub that maintains 2 db of peaking in the frequency response. please note, however, that using r snub attenuates the low-frequency output by a factor of r load /(r snub + r load ). c c = 7pf; r snub = 0 c c = 8pf; r snub = 0 0.1 1000 1 10 100 frequency e mhz gain e db 18 16 14 12 10 8 6 4 2 0 c c = 8pf; r snub = 17.4 499 499 r l 1k 49.9 49.9 c c 33pf fet probe ev s r snub +v s 5 6 figure 15. peaking vs. r snub and c c for c l = 33 pf capacitive load e pf 050 r snub e 20 18 16 14 12 10 8 6 4 2 0 5101 5202530354045 figure 16. relationship of r snub vs. c l for 2 db peaking at a gain of +2
rev. a AD8021 ?20? tp1 ev s +v s gnd p1 r1 non-inv. amplifier logic ref ein +in ev s v out c comp +v s dis AD8021 1 2 3 4 8 7 6 5 +v in r8 0 r7 r1 r23 0 r6 49.9 r25 0 c2 1nf c1 0.1 f c6 r22 0 ev in r20 49.9 r16 inv. amplifier r4 c15 10 f + r21 0 c13 c10 f c9 0.1 f 1 2 3 4 8 7 6 5 c11 r8 0 r11 r3 r2 r26 0 disable r10 0 r9 0 c4 0.1 f c3 1nf r4 0 c8 +v s +out r18 0 r14 0 r15 0 r19 0 c14 c7 r1 eout r12 r13 c16 10 f + ev s c12 1n 0.1 f 1nf c5 sma sma logic ref ein +in ev s v out c comp +v s dis AD8021 figure 17. schematic of evaluation board evaluation board a soic evaluation board is available for the AD8021. the board provides both an inverting and noninverting circuit topology. evaluation board applications referring to the schematic of figure 17, separate sma input connectors and termination resistors are provided for noninverting and inverting amplifiers. separate amplifiers may be used as a differential amplifier as in figure 10. in the differential configuration, either of the input sma connectors may be used and the amplifier inputs connected with r22 and r23. resistors r9, r10, r14, and r15 may be omitted if the default disable mode is used. either amplifier may be disabled from an external source. zero resistors r4, r19, r21, and r23 may be removed to disable one of the amplifiers. for gains of less than 10, refer to figure 4 and table i for the value of the compensation capacitors c6 and c13.
rev. a AD8021 ?21? figure 18. evaluation board silkscreen (top) figure 19. evaluation board layout (top) figure 20. evaluation board layout (bottom) figure 21. evaluation board silkscreen (bottom)
rev. a ?22? AD8021 AD8021 8-lead soic (r-8) dimensions shown in millimeters and (inches) 0.25 (0.0098) 0.19 (0.0075) 1.27 (0.0500) 0.41 (0.0160) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 85 4 1 5.00 (0.1968) 4.80 (0.1890) pin 1 0.1574 (4.00) 0.1497 (3.80) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.33 (0.0130) coplanarity controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-012 aa 8-lead micro_soic (rm-8) dimensions shown in inches and (mm) 0.011 (0.28) 0.003 (0.08) 0.028 (0.71) 0.016 (0.41) 33 27 0.120 (3.05) 0.112 (2.84) 85 4 1 0.122 (3.10) 0.114 (2.90) 0.199 (5.05) 0.187 (4.75) pin 1 0.0256 (0.65) bsc 0.122 (3.10) 0.114 (2.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.94) 0.120 (3.05) 0.112 (2.84) outline dimensions
rev. a ?23? AD8021 revision history location page 6/02?data sheet changed from rev. 0 to rev. a. edits to speci ficati ons ........................................................................................................ ...................................................2
?24? c01888?0?6/02(a) printed in u.s.a.

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